DocumentCode :
2075311
Title :
High-frequency circuit design for 25 Gb/s×4 optical transceiver
Author :
Chujo, Norio ; Takemoto, T. ; Yuki, F. ; Yamashita, Hiromasa
Author_Institution :
Yokohama Res. Lab., Hitachi Ltd., Yokohama, Japan
fYear :
2013
fDate :
22-25 Jan. 2013
Firstpage :
648
Lastpage :
651
Abstract :
A 25-Gb/s optical transceiver module has been developed for backplanes. An optical transceiver for backplanes is necessary to downsize current modules while reducing power consumption and increasing speed up to 25 Gb/s. We employed many approaches to achieve this by reducing crosstalk noise, by enhancing power integrity, and by using CMOS-based analog FE and on-chip termination and optical waveform optimization. The fully integrated transceiver IC was fabricated with the 65-nm CMOS process and the package was small, being 9 × 14 mm in size. We measured the output signal of the transceiver and obtained good eye-openings at 25 Gb/s.
Keywords :
CMOS integrated circuits; optical crosstalk; optical transceivers; CMOS; analog FE; backplanes; bit rate 25 Gbit/s; crosstalk noise; high-frequency circuit design; integrated transceiver IC; on-chip termination; optical transceiver; optical waveform optimization; power consumption; power integrity; size 65 nm; High-speed optical techniques; Integrated optics; Optical amplifiers; Optical crosstalk; Optical device fabrication; Optical interconnections; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
ISSN :
2153-6961
Print_ISBN :
978-1-4673-3029-9
Type :
conf
DOI :
10.1109/ASPDAC.2013.6509672
Filename :
6509672
Link To Document :
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