• DocumentCode
    2075382
  • Title

    Failure Mechanism of stacked CSP module under board-level drop impact

  • Author

    Narravula, Vikram ; Chen, Cheng-fu ; Peterson, Daniel C.

  • Author_Institution
    Dept. of Mech. Eng., Univ. of Alaska Fairbanks, Fairbanks, AK
  • fYear
    2009
  • fDate
    26-29 May 2009
  • Firstpage
    2039
  • Lastpage
    2045
  • Abstract
    Riding chip scale packages (CSPs) in the z-direction enables high-density 3D electronic packaging in which the shorter, through-interposer interconnections can provide faster signal transmission and integrity. Successful applications of such 3D stacking packages require a better understanding of their mechanical responses to and reliability under various loading conditions. In this paper, we present analysis results for failure mechanisms of 3D packaging by (1) simulating detailed mechanical response of the critical joints to a board-level drop impact and identifying the possible failure modes and mechanisms of 95.5Sn4AgCu (SAC) solder joints in 3D stacked-CSP modules under drop impact, and (2) building a theoretical framework that estimates impact-induced stresses in the critical solders. The results suggest the following: (1) Stresses predicted by the theoretical models are on the same order of magnitude as numerical results. (2) Both the theoretical and numerical results show that stresses fluctuate at a higher frequency and are about one order of magnitude smaller in the 90deg orientation drop than in the 0deg drop. The latter implies that all the stack-like 3D packaging reacts dynamically "stifferrdquo in the 90deg drop scheme. This explains why the 0deg drop scheme is the most critical test; if a specimen can survive from the 0deg drop test, it should survive a drop test in any other orientation. (3) The FE results display uneven deformation among the solders of the stack CSP module, in particular in the 0deg orientation drop. We deduce that the unequal deformation among the solders, due to differential flexure between the board and the packages, is the main cause for such high stresses in the critical solders in the 0deg drop. Solders carry impact load more equally and react stiffer in the 90deg orientation drop, resulting in much smaller stresses.
  • Keywords
    chip scale packaging; electronics packaging; solders; board-level drop impact; chip scale packages; failure mechanism; high-density 3D electronic packaging; stacked CSP module; Analytical models; Chip scale packaging; Electronics packaging; Estimation theory; Failure analysis; Predictive models; Soldering; Stacking; Stress; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
  • Conference_Location
    San Diego, CA
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-4475-5
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2009.5074303
  • Filename
    5074303