• DocumentCode
    2075395
  • Title

    Heterogeneous memory management for 3D-DRAM and external DRAM with QoS

  • Author

    Le-Nguyen Tran ; Kurdahi, F.J. ; Eltawil, Ahmed M. ; Homayoun, Houman

  • Author_Institution
    EECS, Univ. of California Irvine, Irvine, CA, USA
  • fYear
    2013
  • fDate
    22-25 Jan. 2013
  • Firstpage
    663
  • Lastpage
    668
  • Abstract
    This paper presents an innovative memory management approach to utilize both 3D-DRAM and external DRAM (ex-DRAM). Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for “latency sensitive”, “bandwidth sensitive”, and “insensitive” applications. To improve the performance and satisfy a certain level of QoS, memory blocks of different application types are allocated differently. Compared to the scratchpad memory management mechanism, the average memory access latency of our approach decreases by 19% and 23%, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover, using our approach, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead, particularly for applications which have high spatial memory locality.
  • Keywords
    DRAM chips; quality of service; 3D-DRAM; QoS; bandwidth sensitive; external DRAM; heterogeneous memory management; innovative memory management approach; latency sensitive; low memory latency; memory access latency; memory block allocation; memory block relocation; multithreaded benchmarks; quality of service; scratchpad memory management mechanism; Bandwidth; Benchmark testing; Computer aided manufacturing; Instruction sets; Memory management; Quality of service; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
  • Conference_Location
    Yokohama
  • ISSN
    2153-6961
  • Print_ISBN
    978-1-4673-3029-9
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2013.6509676
  • Filename
    6509676