Effects of Dit-induced degradation on InGaAs/InAlAs Nanowire Superlattice-FET using Al2O3 and HfO2/La2O3 as gate stacks

In this work we investigate the effects of different interface trap density distributions (D_it) on the electrical and power performances of a Gate-All-Around In_0.53Ga_0.47As/In_0.52Al_0.48As Nanowire Superlattice-FETs (GAA NW SL-FET) using Al₂O₃ and HfO₂/La₂O₃ as gate dielectrics. This analysis shows that a high At content at the high-K/InGaAs interface causes degradation of the subthreshold characteristics and drive current, but also an improvement of the OFF-state leakage. However, even in the presence of traps, dynamic energy/power consumption of the Al₂O₃-based SL-FET is predicted to be at least 2× lower than all the ITRS requirements for the 9nm technology node, while HfO₂/La₂O₃-based device is perfectly suitably for Low-Standby-Power application, at fixed supply voltage V_dd = 0.4 V.