Title :
Strained Si nanowire GAA n-TFETs for low supply voltages
Author :
Luong, G.V. ; Trellenkamp, S. ; Zhao, Q.T. ; Mantl, S. ; Bourdelle, K.K.
Author_Institution :
Peter-Grunberg-Inst., Forschungszentrum Julich, Julich, Germany
Abstract :
In this work we demonstrate strained Si nanowire array n-TFETs with gate all around (GAA) structure yielding ON-currents of 5μA/μm at supply voltage Vdd = 0.5V. Tilted implantation into NiSi2 with BF2 dopant has been used to form a highly doped pocket for the source to channel tunneling junction. Measurements at room temperature indicates sub-threshold slopes (SS) below 60mV/dec for Id <;10-4 μA/μm at Vds =0.1V. For the analog device performance transconductance gm=10 μS/μm, transconductance efficiency gm/Id = 23V-1 and the conductance gd = 0.8μs/μm normalized to the gate width have been extracted under for Vdd=0.5V.
Keywords :
elemental semiconductors; field effect transistors; low-power electronics; nanowires; semiconductor doping; silicon; tunnel transistors; GAA structure; NiSi2:BF2; Si; analog device performance transconductance; channel tunneling junction; doped pocket; gate all around structure; low supply voltages; n-TFET; source tunneling junction; strained silicon nanowire array; sub-threshold slopes; temperature 293 K to 298 K; tilted implantation; tunneling field effect transistors; Junctions; Logic gates; MOSFET; Performance evaluation; Silicon; Transconductance; Tunneling; NiSi2; Si nanowire TFET; analog performance; implantation into silice; low supply voltage;
Conference_Titel :
Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on
Conference_Location :
Bologna
DOI :
10.1109/ULIS.2015.7063774
