Title :
Reviving erroneous stability-based clock-gating using partial Max-SAT
Author :
Bao Le ; Sengupta, Dipak ; Veneris, Andreas
Author_Institution :
ECE Dept., Univ. of Toronto, Toronto, ON, Canada
Abstract :
The conflicting yet increasing demand for high performance and low power in multi-functional chips has pushed techniques for power reduction to the forefront of VLSI design. Although recent developments have automated most of the low power implementations, designers often manually modify the circuit in order to achieve further power savings. This human intervention is often paved with many errors that are bound to typical logic functional failures. Debugging these errors can be a resource intensive process that requires considerable manual effort. This discourages engineers and achieving power savings at the micro level of the design sometimes remains unrealized. This paper proposes a novel debugging methodology to rectify erroneous clock-gating implementations. With the use of Partial Max-SAT, the method localizes and rectifies the design error introduced in the circuit during a clock-gating implementation. The net effect of the proposed methodology leads to shorter debug time ensuring additional power savings. Extensive experiments on benchmark circuits confirm the effectiveness of the approach.
Keywords :
VLSI; integrated circuit design; integrated circuit testing; VLSI design; benchmark circuit; clock gating; clock-gating; erroneous stability; error debugging; logic functional failure; multifunctional chip; partial Max-SAT; power reduction; power saving; resource intensive process; Circuit stability; Clocks; Debugging; Logic gates; Power demand; Registers; Runtime; Clock Gating; Debugging; Design Errors; Low Power design; Max-SAT; Stability Condition;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-3029-9
DOI :
10.1109/ASPDAC.2013.6509685