VRM transient study and output filter design for future processors

In this paper, the transient response of the (voltage regulator module) VRM output voltage when the processor has a fast load change is analyzed. The parasitic parameters play important roles in the transient. The system can be divided into several resonant loops. Each loop can be approximately considered as a decoupled second order system. The transient response is affected by the magnitude of the load change rather than the slew rate of it. Limitations of the present VRM topology for future specifications and output filter design are discussed