VRM transient study and output filter design for future processors

Author

Wong, Pit-Leong ; Lee, Fred C. ; Zhou, Xunwei ; Chen, Jiabin

Author_Institution

Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

Volume

1

fYear

1998

fDate

31 Aug-4 Sep 1998

Firstpage

410

Abstract

In this paper, the transient response of the (voltage regulator module) VRM output voltage when the processor has a fast load change is analyzed. The parasitic parameters play important roles in the transient. The system can be divided into several resonant loops. Each loop can be approximately considered as a decoupled second order system. The transient response is affected by the magnitude of the load change rather than the slew rate of it. Limitations of the present VRM topology for future specifications and output filter design are discussed

Keywords

filters; transient analysis; transient response; voltage regulators; decoupled second order system; fast load change; future processors; output filter design; parasitic parameters; resonant loops; transient response; transient study; voltage regulator module; Capacitors; Circuits; Filters; Power system transients; Process design; Regulators; Resonance; Transient analysis; Transient response; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics Society, 1998. IECON '98. Proceedings of the 24th Annual Conference of the IEEE

Conference_Location

Aachen

Print_ISBN

0-7803-4503-7

Type

conf

DOI

10.1109/IECON.1998.724273

Filename

724273