Title :
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology
Author :
Das, Koushik K. ; Joshi, Rajiv V. ; Chuang, Ching-Te ; Cook, Peter W. ; Brown, Richard B.
Author_Institution :
Michigan Univ., Ann Arbor, MI, USA
Abstract :
This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the VTH and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20× and reduce virtual supply noise by 15%.
Keywords :
CMOS logic circuits; VLSI; circuit optimisation; circuit simulation; integrated circuit design; leakage currents; logic design; low-power electronics; silicon-on-insulator; CMOS; MTCMOS; Si-SiO2; VLSI; footer transistor sizing; header transistor sizing; headers/footers stacking; nano-scale SOI technology; optimal design strategies; stacking height optimization; standby gate leakage reduction; sub-threshold leakage reduction; tapering/sizing ratio; threshold voltage assignment; ultra-low leakage circuits; virtual supply noise reduction; Circuit noise; Contact resistance; Immune system; Noise reduction; Permission; Stacking; Switches; Switching circuits; Transistors; Very large scale integration;
Conference_Titel :
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
1-58113-682-X
DOI :
10.1109/LPE.2003.1231855
