Title :
Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation
Author :
Mukhopadhyay, Saibal ; Roy, Kaushik
Author_Institution :
Dept. of ECE, Purdue Univ., West Lafayette, IN, USA
Abstract :
In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50 nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.
Keywords :
CMOS integrated circuits; MOSFET; Monte Carlo methods; integrated circuit modelling; leakage currents; low-power electronics; nanotechnology; semiconductor device models; sensitivity analysis; tunnelling; 50 nm; 50 nm effective length; Monte Carlo simulation; NMOS device; analytical models; device geometry; doping profile; flat-band voltage; gate leakage; nano-scaled-CMOS devices; process parameter variation; reverse biased source/drain junction band-to-band tunneling; sensitivity analysis; subthreshold leakage; supply voltage; threshold voltage; total leakage current; Analytical models; CMOS process; Doping profiles; Geometry; Leakage current; Nanoscale devices; Semiconductor device modeling; Standards development; Tunneling; Voltage;
Conference_Titel :
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
1-58113-682-X
DOI :
10.1109/LPE.2003.1231856
