Elements of low power design for integrated systems

Author

Kang, Sung-Mo

Author_Institution

California Univ., Santa Cruz, CA, USA

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

205

Lastpage

210

Abstract

The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative developments in low power design recently. Leakage control is becoming critically important for deep sub-100 nm technologies due to the scaling down of threshold voltage and gate oxide thickness of transistors. In this paper, we discuss major sources of power dissipation in VLSI systems, and various low power design techniques on the technology and circuit level, logic level, and system level.

Keywords

CMOS digital integrated circuits; VLSI; integrated circuit design; leakage currents; low-power electronics; CMOS VLSI; circuit level; deep sub-100 nm technologies; gate oxide thickness scaling down; heat dissipation; integrated systems; leakage control; logic level; low power design; portable systems; power consumption; power dissipation sources; system level; technology level; threshold voltage scaling down; very high density VLSI chips; CMOS logic circuits; CMOS technology; Clocks; Energy consumption; Integrated circuit technology; Logic design; Personal digital assistants; Power dissipation; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231863

Filename

1231863