Microarchitecture level power and thermal simulation considering temperature dependent leakage model

Author

Liao, Weiping ; Li, Fei ; He, Lei

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

211

Lastpage

216

Abstract

In this paper, we present power models with clock and temperature scaling, and develop a first-of-its-type coupled thermal and power simulation with a temperature-dependent leakage power model at the microarchitecture level. We show that leakage energy and total energy can be different by up to 2.5× and 2× for temperatures between 90°C and 130°C, respectively. Given such big energy variations, no power model at the microarchitecture level is accurate without considering temperature dependent leakage models.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; circuit simulation; clocks; high-temperature electronics; integrated circuit design; leakage currents; parallel architectures; thermal management (packaging); 90 to 130 C; MTCMOS; SRAM arrays; VLIW architecture; clock gating; clock scaling; coupled thermal power simulation; leakage energy; logic circuits; microarchitecture level power simulation; microarchitecture level thermal simulation; power models; temperature dependent leakage model; temperature scaling; temperature-dependent leakage power model; thermal management techniques; total energy; Circuit simulation; Clocks; Helium; Microarchitecture; Permission; Power system modeling; Temperature dependence; Temperature sensors; Thermal engineering; Thermal management;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231864

Filename

1231864