Title :
A 1.3 μm BiCMOS gate array with configurable on-chip 3-port RAM
Author :
Wong, Thomas ; El-Khatib, Munir
Author_Institution :
Hitachi America Ltd., Brisbane, CA, USA
Abstract :
A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3-μm technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as ×9, ×18, ×36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination
Keywords :
BIMOS integrated circuits; NAND circuits; logic arrays; random-access storage; 0.45 ns; 0.6 pF; 1.3 micron; 4.6 kbit; BiCMOS gate array; SRAM; cell design; configurable on-chip 3-port RAM; memory configuration; memory-plus-logic combination; propagation delay time; two-input NAND; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Capacitance; Clocks; Frequency; Isolation technology; MOS devices; Propagation delay; Variable structure systems;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1989.123187
