A simple compact model for carrier distribution and its application in single-, double- and triple-gate junctionless transistors

We propose a very simple compact model that accurately reproduces the carrier profiles in multiple-gate junctionless transistors. The threshold voltage is easily derived from the carrier distribution. The model takes into account the interaction of the various gates and provides the maximum body size of single- and double-gate transistors enabling full depletion (off-state). TCAD simulations validate the accuracy of our model.