Fast static RAM Level Two cache MCM with gold wire ball bumped flip chip assembly

Author

Higgins, Leo ; Cole, Rebecca ; Duane, Diana

Author_Institution

Adv. Interconnect Syst. Lab., Motorola Inc., Austin, TX, USA

fYear

1997

fDate

18-21 May 1997

Firstpage

511

Lastpage

517

Abstract

The electrical performance benefits afforded by the use of low interconnect parasitic Flip Chip packaging offers even greater system level benefit when used with Multichip Modules (MCM). The flip chip bumping and assembly cost must be minimized for high volume commodity products. An evaluation was undertaken to assess the cost, performance, and reliability of gold wire ball bump assembly for a Level Two cache memory module. The module was already in development with the more standard lead-tin solder based bumping and assembly, and it was desired to determine if gold ball bump bonding could offer any advantages. In this paper, the ball bumps are characterized and the flip chip plastic ball grid array (FC-PBGA) MCM assembly process is described. The test and reliability evaluation plan for the MCM is also discussed

Keywords

SRAM chips; cache storage; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; multichip modules; plastic packaging; Au; Level Two cache MCM; ball bumped flip chip assembly; cache memory module; high volume commodity products; interconnect parasitic; plastic ball grid array; reliability; static RAM; Assembly; Cache memory; Costs; Flip chip; Gold; Multichip modules; Packaging; Read-write memory; Standards development; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1997. Proceedings., 47th

Conference_Location

San Jose, CA

ISSN

0569-5503

Print_ISBN

0-7803-3857-X

Type

conf

DOI

10.1109/ECTC.1997.606217

Filename

606217