High performance matrix multiply using fused datapath operators

The numerous resources on current FPGA devices make them attractive for the implementation of high performance computing and scientific algorithm acceleration. Floating point arithmetic is required for many of these applications, which can be more easily supported by the newer generation of embedded blocks such as larger memories and multipliers. This paper describes a high performance, scalable, dense matrix multiply implementation based on a vector operator function generated with an experimental floating point datapath compiler. Either single precision or double precision datapaths can be compiled, providing in excess of 50 GFLOPs double precision or 100 GFLOPs single precision in Altera Stratix reg III devices. In particular, the contribution of this work is to demonstrate that using fused datapath synthesis for linear algebra applications will allow the entire theoretical floating point capability of the FPGA to be used, and to introduce a benchmark for the correct embedded multiplier to soft logic ratio for these devices.