An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link

Author

Benz, Chuck ; Gowan, Mike ; Springer, Kent

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1991

fDate

12-15 May 1991

Abstract

The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5-μm CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at ECL compatible levels (other portions of the chips operate at 31.25 MHz). IEEE P1149.1 is used for boundary and internal scan. The coding, block diagrams of the chips, CMOS/ECL transceivers, and results are discussed

Keywords

CMOS integrated circuits; data communication equipment; decoding; digital communication systems; digital integrated circuits; encoding; error correction; error detection; optical communication equipment; 1 Gbit/s; 1.5 micron; 31.25 MHz; 93.75 MHz; CMOS process; CMOS/ECL transceivers; ECL compatible levels; IEEE P1149.1; coding; data link; decoder; elasticity buffering; encoder; error detection; error-correcting; fiber optic link; framing; high-speed interface; internal scan; optic fibre link; Clocks; Decoding; Elasticity; Encoding; Error correction; Forward error correction; Logic; Multiplexing; Optical buffering; Optical fibers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164059

Filename

164059