A parallel decoding algorithm of LDPC codes using CUDA

Author

Wang, Shung ; Cheng, Samuel ; Wu, Qiang

Author_Institution

Sch. of Electr. & Comput. Eng., Univ. of Oklahoma-Tulsa, Tulsa, OK

fYear

2008

fDate

26-29 Oct. 2008

Firstpage

171

Lastpage

175

Abstract

A parallel belief propagation algorithm for decoding low-density parity-check (LDPC) codes is presented in this paper based on Compute Unified Device Architecture (CUDA). As a new hardware and software architecture for addressing and managing computations, CUDA offers parallel data computing using the highly multithreaded coprocessor driven by very high memory bandwidth GPU. The parallel decoding algorithm, based on CUDA, allows that all bit-nodes or check-nodes work simultaneously, thus provides an efficient and fast way for implementing the decoder.

Keywords

belief networks; coprocessors; decoding; multi-threading; parity check codes; telecommunication computing; CUDA; Compute Unified Device Architecture; LDPC codes; bit-nodes; check-nodes; graphics processor unit; high memory bandwidth GPU; low-density parity-check codes; multithreaded coprocessor; parallel belief propagation algorithm; parallel data computing; parallel decoding algorithm; Bandwidth; Belief propagation; Computer architecture; Concurrent computing; Coprocessors; Decoding; Hardware; Memory management; Parity check codes; Software architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2008 42nd Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

978-1-4244-2940-0

Electronic_ISBN

1058-6393

Type

conf

DOI

10.1109/ACSSC.2008.5074385

Filename

5074385