Automatic behavioral Verilog model generation using engineering parameters

Proposes a new automatic Verilog model generation method that takes the user-specified engineering parameters as input and generates a behavioral Verilog model. Previous methods require engineers to have knowledge of particular input into techniques such as graphical entry, specialized table format, etc. The proposed method is based on the fact that it is common practice for engineers to specify their circuits using engineering parameters. This parameter-driven method allows engineers to create a Verilog model quickly and easily. Additionally, the proposed method covers a wide range of circuits including commonly-used circuits as well as the finite state machine and the combinational logic block