DocumentCode :
2077251
Title :
Optimal via-shifting in channel compaction
Author :
Cai, Yang ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fYear :
1990
fDate :
12-15 Mar 1990
Firstpage :
186
Lastpage :
190
Abstract :
The authors study the problem of shifting vias to obtain more compactable two-layer channel routing solutions. Let S be a grid-based two-layer channel routing solution. Let vc be the number of grid points on column c that are occupied by vias. Let wc be the number of grid points on column c that are occupied by horizontal wires. They define the height of a column c to be the quantity h c=Avc+Bwc+C , where A, B, C are some design rule dependent constants. A column is said to be critical if it is a column with maximum height. Let HS be the height of the critical column(s) in S. In general, HS is a good measure of the channel height after compaction. They show that the problem of shifting vias to minimize HS can be solved optimally in polynomial time. The complexity of the optimal via-shifting algorithm is O(WL(V+L)log2(V+ L)) where W, L, and V are the number of tracks in S, the number of columns in S, and the number of vias in S, respectively
Keywords :
VLSI; circuit layout CAD; computational complexity; channel compaction; column height; complexity; critical column; design rule dependent constants; grid-based two-layer channel routing; horizontal wires; optimal via-shifting algorithm; polynomial time; Compaction; Polynomials; Routing; Very large scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
Type :
conf
DOI :
10.1109/EDAC.1990.136642
Filename :
136642
Link To Document :
بازگشت