DocumentCode
2077298
Title
CACTUS: a symbolic CMOS two-dimensional compactor
Author
Pérez-Segovia, Thomás ; Joanblanq, Anne-Françoise
Author_Institution
CNET/RCA, Meylan, France
fYear
1990
fDate
12-15 Mar 1990
Firstpage
201
Lastpage
205
Abstract
Describes CACTUS, a two dimensional symbolic compactor that can handle stacking rules, transistors with any shape, long contact plus body-ties. Other features are wire-length minimization, overconstraints relaxation, user-defined constraints, four different types of envelope positioning. CACTUS is internally based on an enhanced virtual grid structure and constraint graphs
Keywords
CMOS integrated circuits; circuit layout CAD; CACTUS; body-ties; constraint graphs; envelope positioning; long contact; overconstraints relaxation; stacking rules; symbolic CMOS two-dimensional compactor; transistors; user-defined constraints; virtual grid structure; wire-length minimization; Compaction; Data structures; Graphics; Human immunodeficiency virus; Pins; Shape; Stacking; Topology; Two dimensional displays; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location
Glasgow
Print_ISBN
0-8186-2024-2
Type
conf
DOI
10.1109/EDAC.1990.136645
Filename
136645
Link To Document