Title :
Verilog HDL based FPGA design
Author :
Gannot, Gary ; Ligthart, Michiel
Author_Institution :
Exemplar Logic Inc., Berkeley, CA, USA
Abstract :
This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) based on the Verilog HDL. It describes aspects of synthesis and optimization specific to FPGAs, in contrast to CMOS gate-arrays. Particular attention is paid to architecture specific optimization, both on register transfer and logic level. The concept of the design methodology is proven by a real-world implementation of an actual design
Keywords :
logic CAD; logic arrays; specification languages; Verilog HDL based FPGA design; architecture specific optimization; field programmable gate arrays; logic level; logic synthesis system; optimization; register transfer level; CMOS logic circuits; Costs; Delay; Design methodology; Field programmable gate arrays; Hardware design languages; High level synthesis; Libraries; Logic arrays; Programmable logic arrays;
Conference_Titel :
Verilog HDL Conference, 1994., International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-5655-7
DOI :
10.1109/IVC.1994.323743
