Title :
Behavioral to structural translation in ESOP form
Author :
Thornton, M.A. ; Nair, V.S.S.
Author_Institution :
Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
Abstract :
A translator for behavioral to structural descriptions of combinational logic circuits is presented. The input is in the form of a Boolean equation using Verilog syntax and the output is a Verilog net-list. The structure of the output circuit is in terms of an Exclusive-OR Sum-of-Products (ESOP) form which is noted for ease of testability and a reduced number of logic gates as compared to traditional Sum-of-Products forms. Also, since many FPGA devices are including the XOR gate as a basic structure, there is interest in ESOP circuit synthesis for FPGA implementations, The numerical methodology used to perform the translation is discussed in detail
Keywords :
Boolean functions; logic CAD; logic arrays; specification languages; Boolean equation; ESOP form; Exclusive-OR Sum-of-Products; FPGA devices; Verilog net-list; Verilog syntax; behavioral to structural translation; combinational logic circuits; ease of testability; translator; Circuit synthesis; Circuit testing; Combinational circuits; Equations; Field programmable gate arrays; Hardware design languages; Logic circuits; Logic devices; Logic gates; Logic testing;
Conference_Titel :
Verilog HDL Conference, 1994., International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-5655-7
DOI :
10.1109/IVC.1994.323747
