Behavioral to structural translation in ESOP form

A translator for behavioral to structural descriptions of combinational logic circuits is presented. The input is in the form of a Boolean equation using Verilog syntax and the output is a Verilog net-list. The structure of the output circuit is in terms of an Exclusive-OR Sum-of-Products (ESOP) form which is noted for ease of testability and a reduced number of logic gates as compared to traditional Sum-of-Products forms. Also, since many FPGA devices are including the XOR gate as a basic structure, there is interest in ESOP circuit synthesis for FPGA implementations, The numerical methodology used to perform the translation is discussed in detail