Modeling techniques to support system level simulation and a top-down development methodology

This paper describes several effective Verilog coding techniques which, by increasing simulation performance, enable a seamless migration of a large scale electronic system through a wide range of abstraction for both the system description and the simulated verification. These coding techniques support the maintenance of design integrity during either forward or backward abstraction migration. This is accomplished by supporting mixed levels of detail for different system functions, and for the same system function at different time periods, during simulation