DocumentCode
2077472
Title
Benchmark descriptions for comparing the performance of Verilog and VHDL simulators
Author
Coumeri, Sari L. ; Thomas, Donald E.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1994
fDate
14-16 Mar 1994
Firstpage
37
Lastpage
42
Abstract
We present a set of benchmarks for comparing the speed of Verilog and VHDL simulators. The benchmarks can be used to evaluate commercial simulators, and can be used to compare results when the translated description is run separately on Verilog and VHDL simulators. This study showed that when comparing high performance simulators for the Verilog and VHDL languages, the VHDL simulator takes between 1.93 and 46.62 times longer to simulate
Keywords
circuit analysis computing; logic CAD; specification languages; VHDL simulators; Verilog; benchmark descriptions; performance; Arithmetic; Arm; Benchmark testing; Computational modeling; Computer simulation; Counting circuits; Hardware design languages; LAN interconnection; Logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Verilog HDL Conference, 1994., International
Conference_Location
Santa Clara, CA
Print_ISBN
0-8186-5655-7
Type
conf
DOI
10.1109/IVC.1994.323750
Filename
323750
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