• DocumentCode
    2077494
  • Title

    Design test-flexible, efficient, and thorough solutions to overcome simulation-to-test roadblocks

  • Author

    Allingham, D. ; Bashford, P. ; Peters, M. ; Vendl, D.

  • Author_Institution
    NCR Microelectron., Ft. Collins, CO, USA
  • fYear
    1989
  • fDate
    25-28 Sep 1989
  • Lastpage
    38018
  • Abstract
    Provided with the proper tools, the ASIC (application-specific integrated circuit) designer can thoroughly address ASIC verification at points early in the design cycle. The capabilities of this type of verification tool set are presented, including an efficient high-level simulation language, software verification of the intended design function, and thorough emulation of tester environments. The roadblocks that stand in the way of successful completion of these simulation-to-test activities are examined. Examples of current simulation-to-test methods and why they are inadequate in circumventing these problems are discussed. A more complete solution to these problems, the NCR Design Test tool set, is presented
  • Keywords
    application specific integrated circuits; circuit CAD; digital simulation; high level languages; software tools; ASIC; NCR Design Test; design cycle; emulation; high-level simulation language; simulation-to-test roadblocks; software verification; tester environments; tool set; verification; Application specific integrated circuits; Automatic testing; Emulation; Logic design; Logic devices; Logic testing; Microelectronics; Software testing; Software tools; Test equipment;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
  • Conference_Location
    Rochester, NY
  • Type

    conf

  • DOI
    10.1109/ASIC.1989.123191
  • Filename
    123191