Fully specified verification simulation

“How to verify a design” becomes the big challenge when Verilog HDL and logic synthesis facilitates the design of highly complex ASIC nowadays. This fully specified verification simulation approach was developed to meet this challenge. During the verification simulation, the fully specified driver not only supplies the stimulus, it also drives the simulator to check the outputs from the circuit under rest. It eliminates the manual check of simulation results. It saves a lot of time in repeating this check for the debugging and verification of different design representations. This approach also improves design quality because the executable fully specified driver can be used as a verification specification document which is so readable that another designer in the team can audit it. Precedence network technique is used to optimize the sequence and concurrence relationship of stimulus tasks and expectation tasks because they are often invoked concurrently. Limitation of Verilog in implementing such concurrence is studied