CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented Lisp

Author

Masson, Christian ; Barbier, Denis ; Escassut, Remy ; Winer, Daniel ; Chevallier, Gregory ; Zeegers, Pierre François

Author_Institution

BULL SA, Les Clayes-sous-Bous, France

fYear

1990

fDate

12-15 Mar 1990

Firstpage

250

Lastpage

256

Abstract

Presents the architecture and capabilities of the CHEOPS floor planning and chip assembly system which was implemented in LeLisp using object-oriented programming. CHEOPS is a highly interactive system which allows the designer to smoothly monitor all the steps from initial floorplanning evaluations down to final chip composition and detailed routing. CHEOPS addresses full custom macro-cell layout. Its major feature is a memory data structure that uniformly models topological relationships and connectivity through all floorplan refinement steps

Keywords

LISP; VLSI; circuit layout CAD; object-oriented programming; CHEOPS; LeLisp; VLSI floor planning; chip assembly system; chip composition; connectivity; custom macro-cell layout; detailed routing; interactive system; memory data structure; object oriented Lisp; object-oriented programming; topological relationships; Assembly systems; Connectors; Data structures; Floors; Graphics; Interactive systems; Monitoring; Routing; Trademarks; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990., EDAC. Proceedings of the European

Conference_Location

Glasgow

Print_ISBN

0-8186-2024-2

Type

conf

DOI

10.1109/EDAC.1990.136654

Filename

136654