DocumentCode :
2077552
Title :
Optimizing compiled Verilog
Author :
Allen, Randy ; McNamara, Michael
fYear :
1994
fDate :
14-16 Mar 1994
Firstpage :
15
Lastpage :
19
Abstract :
While optimization of traditional programming languages is reasonably well understood, optimization of hardware description languages is much less so. Hardware description languages provide both a different set of problems and a different set of opportunities for optimization. On the problem side, hardware models tend to be very large compared to software applications. As a result, the optimizer (which is typically a memory hog even on modest applications) must focus carefully on memory usage. On the opportunity side, hardware models tend to have much simpler control flow than do software applications. This permits a more efficient set of analysis techniques-techniques that are not possible in compilers for high level languages. The paper discusses the ways in which traditional compiler optimization techniques have been adapted in a compiler for Verilog
Keywords :
optimisation; program compilers; specification languages; Verilog; compiler optimization; control flow; hardware description languages; memory usage; optimization; Application software; Art; Computer languages; Hardware design languages; High level languages; Lattices; Mathematical model; Optimizing compilers; Production; Program processors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Verilog HDL Conference, 1994., International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-5655-7
Type :
conf
DOI :
10.1109/IVC.1994.323753
Filename :
323753
Link To Document :
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