Title :
Operating region modeling of deep-submicron CMOS buffers driving global scope inductive interconnects
Author :
Cappuccino, Gregorio
Author_Institution :
DEIS, Calabria Univ., Rende, Italy
Abstract :
The actual operation of a complementary metal-oxide- semiconductor (CMOS) gate driving long resistance-inductance-capacitance (RLC) interconnects is investigated in this paper. Using the alpha-law model, inductance effects of long on-chip interconnects on the operating region of submicron CMOS line-driver transistors is analyzed. A computationally efficient closed form expression for the time the MOS transistors of a line driver actually operate in the saturation region is also presented. The accuracy of the novel expression, particularly suitable for CAD tools implementation, is within 15% as compared to SPICE simulations for a wide range of line parameters.
Keywords :
CMOS integrated circuits; RLC circuits; circuit simulation; superconducting interconnections; CMOS line-driver transistor; alpha-law model; complementary metal-oxide- semiconductor gate; deep-submicron CMOS buffer; global scope inductive interconnect; line parameter; long on-chip interconnect; operating region modeling; resistance-inductance-capacitance; Clocks; Distributed parameter circuits; Driver circuits; Inductance; Integrated circuit interconnections; Power system transients; Power transmission lines; RLC circuits; Semiconductor device modeling; Wire;
Conference_Titel :
Digital System Design, 2003. Proceedings. Euromicro Symposium on
Conference_Location :
Belek-Antalya, Turkey
Print_ISBN :
0-7695-2003-0
DOI :
10.1109/DSD.2003.1231914
