Estimating the utilization of embedded FPGA co-processor

Author

Qu, Yang ; Soininen, Juha-Pekka

Author_Institution

VTT Electron., Oulu, Finland

fYear

2003

fDate

1-6 Sept. 2003

Firstpage

214

Lastpage

221

Abstract

Embedded FPGA co-processors will bring new alternatives for SoC system designers. Comparison of software implementations and reconfigurable hardware implementations will need fast and easy-to-use estimation techniques. In this paper, we present an estimation approach for the resource utilization of the embedded FPGA co-processor. Our approach is based on the principles of high-level synthesis, such as force-directed scheduling, resource allocation, operation assignment and interconnection binding. The method has been applied to simple test cases and a C-language model of MPEG-2 decoder. The average hardware estimation error of MPEG-2 functions was 25%.

Keywords

C language; coprocessors; data flow graphs; field programmable gate arrays; high level synthesis; integrated circuit design; logic partitioning; reconfigurable architectures; system-on-chip; C language model; MPEG-2 decoder; SoC system design; embedded FPGA co-processor; estimation techniques; force-directed scheduling; high-level synthesis; interconnection binding; operation assignment; reconfigurable hardware implementations; resource allocation; resource utilization; Coprocessors; Costs; Embedded software; Field programmable gate arrays; Hardware; Partitioning algorithms; Reconfigurable logic; Resource management; Software maintenance; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design, 2003. Proceedings. Euromicro Symposium on

Conference_Location

Belek-Antalya, Turkey

Print_ISBN

0-7695-2003-0

Type

conf

DOI

10.1109/DSD.2003.1231929

Filename

1231929