DocumentCode
2078881
Title
A dual-port SRAM compiler for 0.8-μm 100 K BiCMOS gate arrays
Author
Dao, Tim ; Svejda, Frank J.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1991
fDate
12-15 May 1991
Abstract
A 6-ns dual-port BiCMOS SRAM compiler has been designed for a 0.8-μm 100K sea-of-gates array. A novel merged bipolar/CMOS memory bit architecture incorporating local interconnect utilizes all base cell transistor sites. Through the use of local interconnect in the memory bit cell, high memory density is achieved. Increased speed is obtained by using bipolar transistors in the memory bit cell, address decoders, and word line drivers. Compiler software can generate RAM instances up to 2K words and 8K total bits
Keywords
BIMOS integrated circuits; SRAM chips; circuit layout CAD; logic CAD; logic arrays; 0.8 micron; 6 ns; 8×103 bit; BiCMOS gate arrays; CAD; SOG array; address decoders; bipolar transistors; bipolar/CMOS memory bit architecture; dual-port SRAM compiler; local interconnect; memory bit cell; sea-of-gates array; word line drivers; BiCMOS integrated circuits; Bipolar transistors; Instruments; Integrated circuit interconnections; Memory architecture; Random access memory; Read-write memory; Routing; Silicon; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.164066
Filename
164066
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