Analytical bounds on the threads in IXP1200 network processor

Author

Ramakrishna, S.T.G.S. ; Jamadagni, H.S.

Author_Institution

Telematics Group, Indian Inst. of Sci., India

fYear

2003

fDate

1-6 Sept. 2003

Firstpage

426

Lastpage

429

Abstract

Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network processors (NP) by L. Geppert (2001) is the blanket name given to the processors, which are traded for flexibility and performance. Network processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design tradeoff, that span in between the custom ASIC and the general-purpose processors. IXP1200 (Intel´s network processor) is one among them. This paper focuses on deriving the analytical bounds on the optimum number of threads in IXP1200 at 1Gbps wire speed.

Keywords

microprocessor chips; multi-threading; packet switching; 1 Gbit/s; ASIC; IXP1200; Internet; design tradeoff; general-purpose processors; multithreaded architectures; network processor; Application specific integrated circuits; Communications technology; Computer architecture; Costs; Delay; Intelligent networks; Memory architecture; Telematics; Wire; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design, 2003. Proceedings. Euromicro Symposium on

Conference_Location

Belek-Antalya, Turkey

Print_ISBN

0-7695-2003-0

Type

conf

DOI

10.1109/DSD.2003.1231976

Filename

1231976