DocumentCode
2079245
Title
An iterative improvement co-synthesis algorithm for optimization of SOPC architecture with dynamically reconfigurable FPGAs
Author
Czarnecki, Radoslaw ; Deniziak, Stanislaw ; Sapiecha, Krzysztof
Author_Institution
Cracow Univ. of Technol., Krakow, Poland
fYear
2003
fDate
1-6 Sept. 2003
Firstpage
443
Lastpage
446
Abstract
In this work, a HW/SW iterative improvement co-synthesis algorithm, which allows for optimization of heterogeneous system architecture with dynamically reconfigurable FPGAs is presented. The algorithm maximizes speed of the system taking into consideration cost constraints.
Keywords
field programmable gate arrays; hardware-software codesign; optimisation; reconfigurable architectures; system-on-chip; SPOC architecture; cost constraints; field programmable gate array; hardware-software iterative improvement co-synthesis algorithm; heterogeneous system architecture optimization; reconfigurable FPGA; systems on programmable chips; Application specific integrated circuits; Computer architecture; Context modeling; Cost function; Electronic mail; Field programmable gate arrays; Hardware; Iterative algorithms; Partitioning algorithms; Software libraries;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design, 2003. Proceedings. Euromicro Symposium on
Conference_Location
Belek-Antalya, Turkey
Print_ISBN
0-7695-2003-0
Type
conf
DOI
10.1109/DSD.2003.1231980
Filename
1231980
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