DocumentCode :
2079629
Title :
An energy-efficient patchable accelerator for post-silicon engineering changes
Author :
Yoshida, Hiroaki ; Fujita, Masahiro
Author_Institution :
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan
fYear :
2011
fDate :
9-14 Oct. 2011
Firstpage :
13
Lastpage :
20
Abstract :
With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5~10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators.
Keywords :
integrated circuit design; system-on-chip; SoC development; control patching mechanism; energy-efficient patchable accelerator; fixed-function accelerators; high-level synthesis; post-silicon engineering changes; post-silicon programmability; programmable accelerators; Memory management; Multiplexing; Registers; Schedules; Scheduling; System-on-a-chip; Engineering change; energy efficiency; high-level synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011 Proceedings of the 9th International Conference on
Conference_Location :
Taipei
Print_ISBN :
978-1-4503-0715-4
Type :
conf
Filename :
6062283
Link To Document :
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