• DocumentCode
    2079949
  • Title

    VLSI-placement based on routing and timing information

  • Author

    Garbers, J. ; Korte, B. ; Prömel, H.J. ; Schwietzke, E. ; Steger, A.

  • Author_Institution
    Forschungsinst. fur Diskrete Math., Bonn, Germany
  • fYear
    1990
  • fDate
    12-15 Mar 1990
  • Firstpage
    317
  • Lastpage
    321
  • Abstract
    The authors propose a hierarchical placement procedure incorporating more and more detailed routing and timing information at increasing levels of the hierarchy. This procedure is based on the well-known min-cut method. A global routing and a timing analysis are computed after every cut and are used to guide the subsequent cell partitioning
  • Keywords
    VLSI; circuit analysis computing; circuit layout CAD; VLSI-placement; cell partitioning; hierarchical placement procedure; min-cut method; routing; timing analysis; timing information; CMOS technology; Cost function; Laboratories; Large-scale systems; Routing; Standards development; Testing; Timing; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1990., EDAC. Proceedings of the European
  • Conference_Location
    Glasgow
  • Print_ISBN
    0-8186-2024-2
  • Type

    conf

  • DOI
    10.1109/EDAC.1990.136666
  • Filename
    136666
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2079949