Fast and accurate activity evaluation in multipliers

This article reports the first results on fast and accurate power evaluation in arithmetic operators. The proposed method uses two steps: 1) accurate useful activity evaluation, 2) fast glitching activity estimation. The first step is based on circuit emulation using FPGA. Activity counters are inserted into the low-level description of the evaluated operator. The modified description is synthesized and downloaded into the FPGA. The operator activity behavior is emulated on the FPGA using large test vectors. The useful activity values accumulated in the FPGA are transferred to the computer. The second step uses the formal model we proposed in for glitching activity estimation. The complete method is demonstrated on basic multipliers.