Title :
Fused floating-point arithmetic for DSP
Author :
Swartzlander, Earl E., Jr. ; Saleh, Hani H.
Author_Institution :
ECE Dept., Univ. of Texas at Austin, Austin, TX
Abstract :
This paper extends the consideration of fused floating-point arithmetic to operations that are frequently encountered in DSP. The fast Fourier transform is a case in point, it uses a complex butterfly operation. For a radix-2 implementation, the butterfly consists of a complex multiply followed by the complex addition and subtraction of the same pair of data. These butterfly operations can be implemented with two fused primitives, a fused two-term inner product and a fused add subtract unit. A floating-point fused FFT Butterfly unit is presented that performs single-precision butterfly floating-point operation in a time that is only 87% the time required for a conventional floating-point butterfly. When placed and routed in a 45 nm process, the fused FFT Butterfly unit occupied about 72% of the area needed to implement a floating-point butterfly using conventional floating-point adders and multipliers. The numerical result of the fused butterfly unit is more accurate because fewer rounding operations are needed.
Keywords :
adders; digital signal processing chips; floating point arithmetic; multiplying circuits; DSP; complex butterfly operation; fast Fourier transform; floating-point adders; floating-point fused FFT butterfly unit; floating-point multipliers; fused floating-point arithmetic; radix-2 implementation; Birth disorders; Digital signal processing; Discrete cosine transforms; Energy consumption; Fast Fourier transforms; Floating-point arithmetic; Hardware; Lakes; Signal processing algorithms; Throughput;
Conference_Titel :
Signals, Systems and Computers, 2008 42nd Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4244-2940-0
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2008.5074512