DocumentCode :
2080419
Title :
Active mitigation of induced phase distortion in a GSM SoC
Author :
Eliezer, Oren ; Staszewski, Bogdan ; Bhatara, Sumeer ; Bashir, Imran ; Balsara, Poras T.
Author_Institution :
Texas Instrum. Inc., Dallas, TX
fYear :
2008
fDate :
June 17 2008-April 17 2008
Firstpage :
17
Lastpage :
20
Abstract :
A novel technique for the mitigation of self-interference in a GSM transmitter is presented. It was designed to mitigate the impact of interference caused by the transmitterpsilas high frequency signals to the on-chip circuitry responsible for generating the PLLpsilas crystal-based reference clock. Excessive jitter experienced in this reference clock causes intolerable modulation distortion, as it is effectively amplified by the PLL that produces the transmitterpsilas modulated carrier. The presented technique, leveraging on specific features of the all-digital PLL (ADPLL), was demonstrated in a GSM system-on-chip (SoC) based on the digital RF processor (DRPtrade) technology in 90 nm CMOS.
Keywords :
cellular radio; distortion; jitter; phase locked loops; radio transmitters; system-on-chip; GSM system-on-chip; GSM transmitter; jitter; modulation distortion; phase distortion; phase locked loops; Circuits; Clocks; Frequency; GSM; Interference; Phase distortion; Phase locked loops; Signal design; Signal generators; Transmitters; All-Digital PLL (ADPLL); Digital RF Processor (DRP); Phase Trajectory Error (PTE); System-On-Chip (SoC); interference mitigation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE
Conference_Location :
Atlanta, GA
ISSN :
1529-2517
Print_ISBN :
978-1-4244-1808-4
Electronic_ISBN :
1529-2517
Type :
conf
DOI :
10.1109/RFIC.2008.4561376
Filename :
4561376
Link To Document :
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