Active mitigation of induced phase distortion in a GSM SoC

A novel technique for the mitigation of self-interference in a GSM transmitter is presented. It was designed to mitigate the impact of interference caused by the transmitterpsilas high frequency signals to the on-chip circuitry responsible for generating the PLLpsilas crystal-based reference clock. Excessive jitter experienced in this reference clock causes intolerable modulation distortion, as it is effectively amplified by the PLL that produces the transmitterpsilas modulated carrier. The presented technique, leveraging on specific features of the all-digital PLL (ADPLL), was demonstrated in a GSM system-on-chip (SoC) based on the digital RF processor (DRPtrade) technology in 90 nm CMOS.