A gate-matrix oriented partitioning approach for multilevel logical networks

A novel approach for gate-matrix synthesis starting from an EDIF logical network description is presented. The networks are automatically decomposed into gate-matrix `macrocells´ with approximately equal layout area using a very effective algorithm, which is adapted to the layout topology, featuring simultaneous module placement in conjunction with a new reliable module area estimation technique. Dramatic improvements in overall layout generation time and layout area are achieved; area savings are significantly higher than previously reported