VLSI Design for DVB-T2 LDPC Decoder

DVB-T2 has adopted powerful LDPC as error correcting codes, which can perform within approximately 1 dB from the Shannon capacity limit, so DVB-S2 has much better communication speed than conventional DVB. In this paper, a low-complexity LDPC decoder for DVB-T2 was designed. With modified layered decoding algorithm, average iterative No. can be decreased by nearly half compared with traditional two-phase message-passing algorithms (TPMP), parallel MDU No. also can be set flexible. When set parallel-ratio=180, system complexity was decreased over 50% compared with conventional 360 parallel-ratio design, whole design have been implemented successfully on Stratix II EP2S130 devices of Altera Corp. Maximum frequency can come to the rate of over 90 MHz, which is significantly sufficient for real-time decoding of DVB-T2 standard.