DocumentCode
2081473
Title
A CMOS 4 ch×1 k time memory LSI with 1 ns resolution
Author
Arai, Yasuo ; Matsumura, Tsuneo ; Endo, Ken-ichi
Author_Institution
KEK, Nat. Lab. for High Energy Phys., Ibaraki, Japan
fYear
1991
fDate
12-15 May 1991
Abstract
A four-channel 1024-b time-to-digital converter chip which records input signals to memory cells at 1-ns intervals, has been developed. The chip was fabricated using 0.8-μm CMOS technology on a 5-mm by 5.6-mm die. It dissipates only 7 mW/channel under typical operating conditions. Tests show that overall linearity and stability are very good
Keywords
CMOS integrated circuits; integrated memory circuits; large scale integration; 0.8 micron; 4 kbit; CMOS technology; LSI; input signals; linearity; memory cells; operating conditions; stability; time-to-digital converter chip; Clocks; Counting circuits; Delay effects; Delay lines; Feedback circuits; Large scale integration; Signal resolution; Threshold voltage; Timing; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.164077
Filename
164077
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