Integrating tools in a VHDL framework

This paper shows the main results after the experience of building tools for VHDL applications using some commercial VHDL front-ends. To this purpose we have evaluated several VHDL analyzers for performance, compliance and application support. This work has been done in order to implement tools based in a formal model of VHDL. We stress the necessity of a safe way to comply with the standard avoiding cumbersome interpretations