Title :
VHDL sign-off simulation: what future?
Author :
Bakowski, Przemyslaw ; Bouchard, Frédérique ; Caïsso, Jean-Paul ; Igier, Frédéric
Author_Institution :
IRESTE, La Chantrerie, France
Abstract :
We are convinced that a universal VHDL gate library for ASIC sign-off simulation can be developed though the optimized VHDL code for various target simulators may differ. Our solution is based on VHDL models written with a unique entity declaration and various architecture bodies targeted at simulators. We concentrate here on VITAL compliant architectures as VITAL should soon become a standard
Keywords :
application specific integrated circuits; circuit analysis computing; formal specification; logic CAD; logic arrays; specification languages; ASIC sign-off simulation; VHDL sign-off simulation; VITAL compliant architectures; entity declaration; optimized VHDL code; universal VHDL gate library; Acceleration; Amplitude shift keying; Application specific integrated circuits; Delay; Kernel; Libraries; Logic design; Standardization; Standards development; Writing;
Conference_Titel :
VHDL International Users Forum. Spring Conference, 1994. Proceedings of
Conference_Location :
Oakland, CA
Print_ISBN :
0-8186-6215-8
DOI :
10.1109/VIUF.1994.323956
