Integrating hierarchical test benches into an evolving VHDL design environment

Flexible, hierarchical test benches are developed naturally as part of the normal model development process and support VHDL, WAVES, and company-proprietary standards. The integration of these tool-automated VHDL test benches is described. In TI-Microelectronics, automated development of VHDL test benches and integration of test bench development into the VHDL modeling process are being employed successfully. The novel hierarchical structuring technique described integrates automated VHDL test bench capabilities with the historical TI proprietary design environment