DocumentCode
2082049
Title
A digitally calibrated 64.3–66.2GHz phase-locked loop
Author
Tsai, Kun-Hung ; Wu, Jia-Hao ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
fYear
2008
fDate
June 17 2008-April 17 2008
Firstpage
307
Lastpage
310
Abstract
In this paper, a 64.3-66.2 GHz digitally calibrated phase-locked loop (PLL) is presented in 0.13 mum CMOS technology. A digital calibration circuit is adopted to align the center operation frequency between the VCO and the divider. At 64.3 GHz, the measured phase noise at 1 MHz offset is 84.1 dBc/Hz. The PLL consumes 72 mW without output buffers from 1.2 V supply.
Keywords
CMOS integrated circuits; calibration; dividing circuits; noise measurement; phase locked loops; phase noise; voltage-controlled oscillators; CMOS technology; VCO; digital calibration circuit; divider; frequency 1 MHz; frequency 64.3 GHz to 66.2 GHz; phase noise measurement; phase-locked loop; power 72 mW; size 0.13 mum; voltage 1.2 V; Calibration; Capacitors; Circuits; Clocks; Frequency conversion; Millimeter wave communication; Millimeter wave technology; Phase locked loops; Voltage-controlled oscillators; Wireless communication; CMOS; Phase-locked loop; clock generator; digital calibration; frequency divider;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE
Conference_Location
Atlanta, GA
ISSN
1529-2517
Print_ISBN
978-1-4244-1808-4
Electronic_ISBN
1529-2517
Type
conf
DOI
10.1109/RFIC.2008.4561442
Filename
4561442
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