A data-driven algorithm and systolic architecture for image morphology

The paper presents a systolic processor for binary and gray scale morphological operations. The principle of the proposed implementation scheme is based on an input data-driven algorithm: the envelope scan method (ESM) in cooperation with a new formalization of the window-operation provides promising, cost-effective logic gate implementation introduced as the envelope scan processor (ESP). It is showed that the proposed architecture can also be easily applied to adaptive operations, since the SE-adaptation is directly supported by the algorithm. Analysis shows that the ESP offers remarkable results in terms of the utilized logic components in comparison to other recent processor designs