Title :
Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes
Author :
Studer, C. ; Preyss, N. ; Roth, C. ; Burg, A.
Author_Institution :
Integrated Syst. Lab., ETH Zurich, Zurich
Abstract :
We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11 n standard and achieves a throughput of 780 Mbit/s with a core area of 3.39 mm2 in 0.18 mum CMOS technology.
Keywords :
CMOS integrated circuits; VLSI; parity check codes; telecommunication standards; wireless LAN; CMOS technology; IEEE 802.11n standard; LDPC codes; VLSI implementation; decoder architecture; hardware architecture; low-density parity check decoder; quasicyclic codes; reconfigurable decoder; size 0.18 mum; Application specific integrated circuits; CMOS technology; Code standards; Decoding; Message passing; Parity check codes; Sparse matrices; Throughput; Very large scale integration; Wireless communication;
Conference_Titel :
Signals, Systems and Computers, 2008 42nd Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4244-2940-0
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2008.5074592
