Title :
A low power DSP core for an embedded MP3 decoder
Author :
Lai, Dishi ; Lin, Quan ; Chen, Sizhong ; Margala, Martin
Author_Institution :
ECE Dept., Rochester Univ., NY, USA
Abstract :
A low power 32-bit 20 MIPS DSP core designed for MPEG1 Audio Layer III (MP3) decoder is proposed. It has an architecture designed specifically for MP3 decoding algorithm implementation. The authors used the instruction level clock gating technique to achieve lower power for portable applications besides other effective dynamic power management schemes. A 0.25 μm, 2.5 V CMOS process was used
Keywords :
CMOS integrated circuits; audio coding; clocks; decoding; digital signal processing chips; 0.25 micron; 2.5 V; 20 MIPS; 32 bit; CMOS process; MP3 decoding algorithm; MPEG1 Audio Layer III; dynamic power management; embedded MP3 decoder; instruction level clock gating technique; low power DSP core; portable applications; CMOS process; Clocks; Decoding; Digital audio players; Digital signal processing; Digital signal processing chips; Energy management; Hardware design languages; Pipelines; Registers;
Conference_Titel :
Industrial Electronics Society, 2001. IECON '01. The 27th Annual Conference of the IEEE
Conference_Location :
Denver, CO
Print_ISBN :
0-7803-7108-9
DOI :
10.1109/IECON.2001.975579
