A 1.6-to-3.2/4.8 GHz dual-modulus injection-locked frequency multiplier in 0.18μm digital CMOS

This paper proposes a variable-modulus injection-locked frequency multiplier for better harmonic suppression. It is more suitable for fully-integrated implementation using low-Q on-chip inductors in digital CMOS than conventional approaches. A prototype dual-modulus frequency doubler/tripler with 1.6 GHz input and 3.2 GHz/4.8 GHz output is implemented in a 0.18 mum standard digital CMOS. At 5% locking range, the doubler mode achieves fundamental suppression of 42 dB with 2.2 mW power consumption from 1 V supply; while the tripler mode achieves 40 dB suppression at the fundamental and 32 dB at the second harmonic, with 3.7 mWpower consumption from 1 V supply. Good phase noise performance is achieved for both doubler and tripler modes.