DocumentCode
2083054
Title
Isolation enhancement in integrated circuits using dummy metal fill
Author
Gaskill, Steven G. ; Shilimkar, Vikas S. ; Weisshaar, Andreas
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
fYear
2008
fDate
June 17 2008-April 17 2008
Firstpage
483
Lastpage
486
Abstract
Metal fill patterning in modern IC processes is often viewed as parasitics to be minimized. Here, we use metal fills to improve isolation. The improved isolation comes at the cost of increased capacitive loading. This isolation-loading tradeoff is analyzed for various grounding strategies. It is found to be best to ground first inner metal-fill. The effect of finite ground impedance is analyzed. An assumed worst-case ground impedance path of 50Omega is shown to give sufficient grounding up to 10 GHz.
Keywords
chemical mechanical polishing; integrated circuits; isolation technology; dummy metal fill; integrated circuits; isolation enhancement; metal fill patterning; Capacitance; Chemical processes; Computer science; Copper; Costs; Dielectrics; Fabrication; Grounding; Impedance; Radio frequency; CMP; Grounding; Isolation; Metal Fill; Shielding;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE
Conference_Location
Atlanta, GA
ISSN
1529-2517
Print_ISBN
978-1-4244-1808-4
Electronic_ISBN
1529-2517
Type
conf
DOI
10.1109/RFIC.2008.4561482
Filename
4561482
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